As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field-effect transistors (Fin FETs). In a Fin FET, a gate electrode is adjacent to two side surfaces of a channel region with a gate dielectric layer interposed between them. On a top surface of the channel of a Fin FET, a passivation layer is formed between the gate electrode and the dielectric layer. In a tri-gate Fin FET (T-Fin FET), the additional passive layer is not formed and the gate structure surrounds (wraps) the fin on three surfaces and the transistor essentially has three gates controlling the current through the fin or channel region. Beyond 14 nm technology node, the epi source or drain structure introduces serious issues for fin pitch scaling. The source and/or drain sheet resistance and contact resistivity can play a critical role when the device area is scaling. Solutions are required that can efficiently resolve the resistance degradation by area shrinking.